The School of Electronics & Communication Engineering, Shri Mata Vaishno Devi University (SMVDU), Katra, organised an industrial visit to Semi-Conductor Laboratory, Chandigarh, Department of Space, Government of India for its MTech students to focus on design, development, fabrication, assembly and packaging, testing and quality assurance of CMOS and MEMS devices for satellite and other various applications.
This industrial visit was coordinated by Dr Sachin Kumar Gupta, faculty, SoECE and Shaivya Manhas,faculty, SoEM, along with BK Bhatia, T&P officer, SMVDU. The visit started with the brief profile of SCL by Sanjay Bhatnagar, Engineer SF’— PPMD at Semi-Conductor Laboratory.
He presented a short video clip pertaining to major contributions, achievements, and campus life of SCL. Later, he discussed the design process for fabrication of ICs, mixed signal and analog ASIC design, and wide spectrum industry standard EDA tools.
The students were taken to various labs which includes 8’’ wafer fabrication facility (clean rooms of class 1, 10, 100 and 1000 with controlled environmental conditions), assembly and packaging (fine pitch bonding capability for pad size of 57µmx57µm and 65µm pitch, low temperature process for packaging large dies, multi-chip packaging process for ASICs and sensor devices, MIC packaging), reliability & quality assurance (facility for environmental test, facility for failure analysis) and others. The industrial tour was very informative, enriching, and imparted a great learning experience to the students.
